Basic UVM testbench for a Stream Processor
Other projects
next section →
This page: A specific testbench


A specific testbench

This page is getting shorter as more and more comments are put into the testcode. A simple testbench for the 8-oneproc HWSP was put together to get the communication issues sorted out enough where the HWSP was at least going through the motions of working. That testbench is here:, but it is ancient and is woefully out-of-sync with the current much-improved oneproc design.

The oneproc unit testbench is here: and will run the tests listed at the beginning of There are the bringup tests only and more tests are on the way.

Because of the close relationship between the oneproc interface and the HWSP top level interface, only the oneproc testbench will be discussed here. The scoreboard, for example, will be identical for the two testbenches; they will just get their transactions from a different analysis port.

There are 4 basic transactions all extended from Base_txn or Result_txn.
There are 4 basic sequences, WRITE_REQ, READ_REQ, WRITE, and READ.
The WRITE_REQ and READ_REQ merely ensure the DUT is ready for WRITE and READ, but perform no data access themselves.
The READ transaction reads out the data record and a read channel monitor creates a Result_txn which is sent to the scoreboard.
The WRITE and READ transactions are awkward. As described in detail in The generic testbenches, the read and write sequences are designed to mimic what would be actual external interfaces. Those connections will have knowledge of the type of data access to perform, and so must also the testbench.

This is a work in progress