The Specification

General points, terminology, and notation

• unproblematic correct usage normal cases and acceptable misuse,
• specific cases of protocol violation,
• specific tests of computation accuracy,
• specific situations the random can't hit before my patience runs out,

• write channel attempts to overfill HWSP with tasks (as one would test a FIFO by trying to write while it was full),
• coordinated write/read side attempts to give HWSP all situations of a single task to the maximum number of tasks (like filling a FIFO),
• read side attempts to keep HWSP empty of tasks acknowledging as fast as possible (like draining and trying to "pull" from an empty FIFO) ,
• read side attempts to block HWSP writes even when all tasks are complete (making sure the throttling mechansim works).

• write and read channel use and abuse,
• computation tests,
• attempts to elicit coverpoint hits of the HWSP internal assertions,
• generally, attempt to elicit incorrect behavior of the HWSP DUT.

Stream Processor Functions

Embedded side note: Anyone trying to "idiot proof" something like a GUI knows that there is often more code involved in sanitizing input and making certain that user choices make sense than there is code in the actual function. I don't want to put that sort of checking in the hardware. All I ask of the hardware is that complete gracefully in a reasonable amount of time, even when given rubbish commands and/or data.

The Stream Processor

Block Diagram: Stream Processor

interface HWSP_sys_if ; logic clock ; logic reset ; logic setLoadMode ; logic getLoadMode ; logic abort ; logic idle ; endinterface interface HWSP_write_if ; logic [7:0] frameID_wOut ; logic okToWrite ; logic writeReq ; logic readyToWrite ; logic [3:0] wAddr ; logic [31:0] wData ; logic write ; endinterface

interface HWSP_read_if ; logic [7:0] frameID_rOut ; logic finalBit ; logic okToRead ; logic readReq ; logic readyToRead ; logic read ; logic [3:0] rAddr ; logic [31:0] rData ; endinterface

Signal Description: Stream Processor

Bus Transfers: Stream Processor

N.B. In the diagrams below, the arcs indicate control flow. All inputs are sampled on the rising edge of the clock and all outputs derive from the rising edge of the clock. In the example to the right the input edge at 'a' is sampled at 'c', and the output change at 'b' is the result following the clock at 'c'.

    Reset
The figure below shows the proper reset sequence. Assert as you will, but make reset deassertion synchronous. reset must be asserted for at least one clock cycle.


[l] VID_SP_func_assert_resetDeassertNotSynchronous_ERR
Note: The reset signal will be left out of all following diagrams.

    Load mode
The input setLoadMode is a request. In order for the SP to use a mode, the output getLoadMode must be in that state. This diagram shows the correct sequence for changing the load mode. setLoadMode can only be changed when idle is asserted.


[l] VID_SP_func_assert_setLoadModeParallelAttempted
[l] VID_SP_func_assert_setLoadModeNotIdle_ERR
[l] VID_SP_func_assert_getLoadModeIsSet_ERR

    abort and idle
The assertion of abort will cause all processors in the SP to abort their current task. idle is a logical AND of all the available signals from the oneproc units in the SP, so it will assert following the last processor to respond to the assertion of abort. It is expected that abort will be held until the assertion of idle. The deassertion of abort is only required in order to recommence task assignments.


[l] VID_SP_func_assert_normalAbort
[l] VID_SP_func_assert_abortDeassertBeforeIdle_ERR
[l] VID_SP_rand_assert_cprop_abortWithinXYZ

    Normal write sequence
A write can be initiated when readyToWrite is asserted. A write request via writeReq can be asserted before or after the signal okToWrite is asserted as shown in the two diagrams below. Note that the assertion of okToWrite is completely unrelated to the assertion of writeReq. The okToWrite is internally controlled and is asserted as a result of at least one processor being free to be assigned a new task. Assertion of writeReq in the same cycle of okToWrite is also legal as the two are independent.

writeReq before okToWrite




okToWrite before writeReq

With readyToWrite asserted writes can be initiated. The SP looks like a 16 x 32-bit word positive-edge synchronous RAM. Just write to it. The processor being assigned the task will begin on the deassertion of writeReq. Note that there is actually no requirement to do any writing (asserting of write). If one wishes the same computation be performed and the same frameID used, just deassert writeReq immediately following the assertion of readyToWrite. If one is tracking tasks then one should at least change the frameID with a write to byte0 of word 0.


[D] VID_SP_func_assert_writeReqBeforeOkToWrite
[D] VID_SP_func_assert_writeReqAfterOkToWrite



[D] VID_SP_func_assert_readyToWriteLeadsWriteReq_ERR

    Illegal removal of writeReq
This is is illegal, but should not cause a hang.


[D] VID_SP_func_assert_writeReqWithdrawnOK
[D] VID_SP_func_assert_writeReqWithdrawnAfterReadyToWrite_ERR

    Normal read sequence
A read can be initiated when readyToRead is asserted. The read request via readReq can be asserted before or after the signal okToRead is asserted as shown in the two diagrams below. Note that the assertion of okToRead is completely unrelated to the assertion of readReq. okToRead is internally controlled and indicates only that at least one processor has completed its task and has results available. Assertion of readReq in the same cycle of okToRead is also legal as the two are independent.

readReq before okToRead


okToRead before readReq

With readyToRead asserted a read can be initiated. The SP looks like a 16 x 32-bit word positive-edge synchronous RAM. Just read it. The processor selected will become free on the deassertion of readReq.



[D] VID_SP_func_assert_readyToReadLeadsReadReq_ERR

Here is a normal read sequence. The value of finalBit and frameID_rOut are not considered.

Note that there is actually no requirement to do any reading (asserting of read) ... the results can be:

actually not in the internal memory. The task could be performed in external memory.

So no read is required, only the deassertion readReq following the assertion of readyToRead. Actually reading the contents of the currently pointed-to oneproc is up to the overall computational task. For repeated computations, such as in pipelining, the finalBit and frameID_rOut are provided. For example, in the diagram below the state of the finalBit and perhaps the value of frameID_rOut told the scheduler that no read was required ... only an acknowledgement in the form of deassertion of readReq.


[D] VID_SP_func_assert_readReqBeforeOkToRead
[D] VID_SP_func_assert_readReqAfterOkToRead

    Illegal removal of readReq
NOTE: FIXME check behavior of RTL in this case. It is illegal, but should not cause a hang.

[D] VID_SP_func_assert_readReqWithdrawnOK
[D] VID_SP_func_assert_readReqWithdrawnAfterReadyToRead_ERR

 
 

---

The oneproc unit

Block Diagram: oneproc unit

interface oneproc_if ; logic clock ; logic reset ; logic abort ; logic [7:0] frameID_wOut ; logic available ; logic load ; logic write ; logic run ; logic [3:0] wAddr ; logic [31:0] wData ; (cont ...)

(... cont) logic [7:0] frameID_rOut ; logic finalBit ; logic done ; logic thanks ; logic read ; logic [3:0] rAddr ; logic [31:0] rData ; endinterface

 
 
 

Signal Description: oneproc unit

All signals are active high.
Direction is given w.r.t the oneproc unit.
 
 

System control group

Name	Direction	Description
clock	input	system clock. All signals sampled or transition w.r.t. clock's rising edge.
reset	input	system reset. Synchronous deassert. Verify the device comes out of reset, and not just at the beginning of the simulation. [ ] VID_OP_func_assert_resetDeassertNotSynchronous_ERR
abort	input	This signal is identical in function and wiring to the SP level signal abort. 0 - Not an abort. 1 - Assert to abort all processing. In response, the available is asserted to indicate that this oneproc is available. This signal can be asserted at any time and must be held until available is asserted. The oneproc will go available within YYY clocks following the assertion of abort. [ ] VID_OP_func_assert_normalAbort [ ] VID_OP_func_assert_abortDeassertBeforeIdle_ERR, [ ] VID_OP_rand_assert_cprop_abortWithinYYY Abort is not an exceptional behavior, but is expected to occur often. It should be tested as such, at least 5% of the time.

 
 
 
 

Write control group

Name	Direction	Description
frameID_wOut	output	This is the frameID of the processor, reflected back to an output. [*] VID_OP_func_assert_frameID_wOutExported
available	output	0 - this processor is busy. 1 - this processor is idle and can be given a new task. This can happen because the unit completed and has been acknowledged, or as a response to an abort. Asserting write or load before available should have no affect. Asserting write and load simultaneously with the assertion of available is legal and has the same behavior as asserting write and load following available. If available is deasserted, only the assertion of thanks will cause available to be asserted again. [*] VID_OP_func_assert_availableDeassertOnWrite [i] VID_OP_func_assert_writeWithAvailable [D] VID_OP_func_assert_writeBeforeAvailable_ERR
load	input	0 - Not a load. 1 - This signal controls the steering logic in the oneproc unit. Both the write channel and the computation function have access to the internal memory for the DataRec, and the load is essentially the multiplexor select line. When asserted, the internal memory is available for writing on the assertion of the write signal. [D] VID_OP_func_self_writeWithoutLoad [D] VID_OP_func_self_writeWithoutLoad_ERR
write	input	0 - not a write. 1 - This is effectively the write signal from the SP top level. When asserted with load, place the data on wData at the address of wAddr into the internal memory. It is illegal to assert write unless a valid write cycle is in progress marked by load && available, although there should be no affect of doing so. [D] VID_OP_func_assert_writeB4available_ERR [D] VID_OP_func_self_loadWithoutWrite [D] VID_OP_func_self_loadWritesInParts [D] VID_OP_func_assert_writeWithoutLoad_AvailableDoesNotDeassert [D] VID_OP_func_assert_writeReqWithdrawnAfterReadyToWrite_ERR
run	input	0 - Not run. 1 - asserted for one or two clocks, this starts the oneproc unit to initiate the computation in accordance with the contents of the data frame written to its memory. Run must be deasserted nCDXYE cycles before the processor is done, so just assert it for one or two clocks and let the processor do its thing. I am not going to deal with what happens when run is held asserted, so it will be an error to assert run for more than two cycles. [ ] VID_OP_func_assert_loadToAvailableDeassertDelay_ERR [ ] VID_OP_func_assert_neverCalculateWithoutRun_ERR [D] VID_OP_func_assert_runHeldAsserted_ERR
[3:0] wAddr	input	In this particular oneproc unit the internal memory is 64 bytes organized as 16 32-bit words. wAddr presents the one-of-16 address. wAddr is sampled on the rising edge of the clock when write && load are asserted.
[31:0] wData	input	In this particular oneproc unit the internal memory is 64 bytes organized asa 16 32-bit words. rData presents the 32-bit word. wData is sampled on the rising edge of the clock when write is asserted with load asserted.

 
 
 
 

Read control group

Name	Direction	Description
finalBit	output	This is bit 7 of the most recent value written to the command field. [*] VID_OP_func_assert_finalBitFollows
done	output	0 - not done. 1 - this processor is done performing the computation and waiting for an acknowledgement via an assertion of thanks. done remains asserted until thanks is asserted for one or more clocks. The expectation is that results will be read, although an actual read is not necessary to clear done and free this processor for other processing, only a thanks is required. [D] VID_OP_func_assert_readBeforeDone
thanks	input	0 - not thanking. 1 - acknowledge this processor and free it for other processing. Assertion of thanks deasserts available. Assertion of thanks has no effect unless available is asserted. [t] VID_OP_func_assert_thanksWithoutRead [D] VID_OP_func_assert_thanksWithAvailableDeasserted [ ] VID_OP_func_assert_thanksToAvailableDeassertDelay_ERR
read	input	0 - Not a read. 1 - When asserted, read the data from the address rAddr and place it on rData. It is silly to assert read unless a valid read cycle is in progress marked by done. [D] VID_OP_func_self_sillyRead [D] VID_OP_rand_assert_sillyRead
[3:0] rAddr	input	The internal memory for this particular oneproc unit is 64 bytes organized as 16 32-bit words. rAddr presents the one-of-16 address. rAddr is sampled on the rising edge of the clock when read is asserted.
[31:0] rData	output	The internal memory for this particular oneproc unit is 64 bytes organized as 16 32-bit words. rData returns a 32-bit word. rData is produced from the rising edge of the clock when read is asserted.

 
 
 

Bus Transfers: oneproc unit

System

    abort and available
The assertion of abort will cause the oneproc unit to abort its current task. available is asserted when the oneproc unit has responded to the abort. It is expected that abort will be held until the assertion of available. The deassertion of abort is only required in order to use the oneproc unit, otherwise the oneproc will behave as though in reset and be unresponsive.

[ ] VID_OP_func_assert_normalAbort
[ ] VID_OP_func_assert_writeWhileInAbort
[ ] VID_OP_func_assert_abortDeassertBeforeIdle_ERR
[ ] VID_OP_rand_assert_cprop_abortWithinYYY



 
 
 
  Write channel usage

    Normal write sequence
The oneproc unit can be written to after available is asserted. To write to the processor, assert load with wAddr and associated wData. It's a RAM, so order of writes is not important. To start the processor deassert write and load and assert run. Those can occur in the same cycle. The unit deasserts available on the first occurence of load. The oneproc unit should ignore the write signal after run is asserted and until the next assertion of available.


[D] VID_OP_func_assert_assertRunWithWriteAsserted_ERR
[D] VID_OP_func_assert_assertRunWithLoadAsserted_ERR
[D] VID_OP_func_assert_assertRunAfterLoad
[D] VID_OP_func_assert_assertWriteWhileRunning_ERR
[D] VID_OP_func_assert_loadToAvailableDeassertDelay_ERR

 
 
 
  Read channel usage

    Normal read sequence
A read can be initiated when done is asserted. A read is an assertion of read with the desired rAddr. rData follows in the next cycle. Zero or more reads are required. In order to free the processor, say thanks by asserting thanks.


[ ] VID_OP_func_assert_thanksToAvailableAssertDelay_ERR

    Null read sequence
A null read is performed by saying thanks following the assertion of done.


[D] VID_OP_func_assert_thanksOnNullRead

 
 
 

---

List of all VIDs

[D] VID_OP_func_assert_writeBeforeAvailable_ERR<

oneproc level tests
[ ] VID_OP_func_assert_abortDeassertBeforeIdle_ERR	oneproc_abort_test	-
[ ] VID_OP_func_assert_readB4OKandReady_ERR	oneproc_badProtocol_1_test	-
[ ] VID_OP_func_assert_readReqWithdrawnAfterReadyToRead_ERR	oneproc_badProtocol_1_test	-
[ ] VID_OP_func_assert_resetDeassertNotSynchronous_ERR	oneproc_badProtocol_1_test	-
[ ] VID_OP_func_assert_loadToAvailableDeassertDelay_ERR	oneproc_badProtocol_1_test	-
[ ] VID_OP_func_assert_thanksToAvailableAssertDelay_ERR	oneproc_badProtocol_1_test	-
[ ] VID_OP_func_assert_thanksToAvailableDeassertDelay_ERR	oneproc_badProtocol_1_test	-
[D] VID_OP_func_assert_writeB4available_ERR	oneproc_badProtocol_1_test	-
[ ] VID_OP_func_assert_writeB4OKandReady_ERR	oneproc_badProtocol_1_test	-
[D] VID_OP_func_assert_writeWithoutLoad_AvailableDoesNotDeassert	-
[D] VID_OP_func_assert_writeReqWithdrawnAfterReadyToWrite_ERR	oneproc_badProtocol_1_test	-
[ ] VID_OP_func_assert_thanksOnNullRead	oneproc_SMOOTH_1_pipeline_final_test	-
[ ] VID_OP_func_assert_assertRunAfterLoad	oneproc_SMOOTH_0_pipeline_test oneproc_SMOOTH_1_pipeline_test oneproc_SMOOTH_1_pipeline_final_test	-
[ ] VID_OP_func_assert_assertRunAfterLoad	oneproc_SMOOTH_0_pipeline_test oneproc_SMOOTH_1_pipeline_test oneproc_SMOOTH_1_pipeline_final_test	-
[*] [ ] VID_OP_func_assert_frameID_wOutExported	oneproc_CMMD_mix_1_test	oneproc_if
[ ] VID_OP_func_assert_normalAbort	oneproc_abort_test	-
[ ] VID_OP_func_assert_readReqAfterOkToRead	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_func_assert_readReqB4okToRead	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_func_assert_frameID_rOutFollows	oneproc_CMMD_mix_1_test	-
[*] VID_OP_func_assert_finalBitFollows	oneproc_SMOOTH_1_pipeline_final_test	-
[ ] VID_OP_func_assert_readReqBeforeOkToRead	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_func_assert_readReqWithdrawnOK	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_func_assert_loadWritesInParts	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_func_assert_writeReqB4okToWrite	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_func_assert_loadWithoutWrite	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_func_assert_availableDeassertOnWrite	oneproc_ProtocolVariations_1_test	-
-
[*] VID_OP_func_self_pipeline [*] VID_OP_func_self_pipeline_nullWithFinal [ ] VID_OP_func_self_pipeline_ChangeCMMD	oneproc_SMOOTH_0_pipeline_test oneproc_SMOOTH_1_pipeline_test oneproc_SMOOTH_1_pipeline_final_test	-
[ ] VID_OP_func_assert_readyToWriteLeadsWriteReq_ERR	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_func_assert_readyToReadLeadsReadReq_ERR	oneproc_ProtocolVariations_1_test	-
[ ] VID_OP_rand_assert_cprop_abortWithinYYY	placeholdernameoftest	-
[ ] VID_OP_rand_assert_CMMDtoAvailableInMclocks	placeholdernameoftest	-
[D] VID_OP_rand_assert_sillyRead	placeholdernameoftest	-
[ ] VID_OP_rand_ccover_assert_abortToavailableTime	placeholdernameoftest	-
[ ] VID_OP_func_cover_abort	oneproc_abort_test	-
[ ] VID_OP_func_self_CORRearlyDoneOnArg1match	oneproc_CORR_1_single_test	-
[ ] VID_OP_func_self_CORRmatch	oneproc_CORR_0_single_test oneproc_CORR_1_single_test	-
[ ] VID_OP_func_self_NOPdoesNotChangeDataRecord	oneproc_NOP_test	-
[ ] VID_OP_func_self_BadCMMD	oneproc_BADCMMD_test	-
[D] VID_OP_func_self_writeWithoutLoad	-
[D] VID_OP_func_self_writeWithoutLoad_ERR	-
[D] VID_OP_func_self_loadWritesInParts	-
[D] VID_OP_func_self_loadWithoutWrite	-
[ ] VID_OP_rand_self_pipeline	placeholdernameoftest	-
HWSP level tests
[l] VID_SP_func_assert_abortDeassertBeforeIdle_ERR	placeholdernameoftest
[l] VID_SP_func_assert_getLoadModeIsSet_ERR	placeholdernameoftest
[D] VID_SP_func_assert_readB4OKandReady_ERR	placeholdernameoftest
[D] VID_SP_func_assert_readReqWithdrawnAfterReadyToRead_ERR	placeholdernameoftest
[l] VID_SP_func_assert_readyToReadMoreThanYclocks_ERR	placeholdernameoftest
[l] VID_SP_func_assert_readyToWriteMoreThanXclocks_ERR	placeholdernameoftest
[l] VID_SP_func_assert_resetDeassertNotSynchronous_ERR	placeholdernameoftest
[l] VID_SP_func_assert_setLoadModeNotIdle_ERR	placeholdernameoftest
[D] VID_SP_func_assert_writeReqWithdrawnAfterReadyToWrite_ERR	placeholdernameoftest
[l] VID_SP_func_assert_frameID_wOutFollows	placeholdernameoftest
[l] VID_SP_func_assert_idleFollowsAbort	placeholdernameoftest
[l] VID_SP_func_assert_idleFollowsAllProcsDone	placeholdernameoftest
[l] VID_SP_func_assert_normalAbort	placeholdernameoftest
[D] VID_SP_func_assert_readReqAfterOkToRead	placeholdernameoftest
[D] VID_SP_func_assert_readReqB4okToRead	placeholdernameoftest
[D] VID_SP_func_assert_readReqBeforeOkToRead	placeholdernameoftest
[l] VID_SP_func_assert_frameID_rOutFollows	placeholdernameoftest
[l] VID_SP_func_assert_finalBitFollows	placeholdernameoftest
[D] VID_SP_func_assert_readReqWithdrawnOK	placeholdernameoftest
[l] VID_SP_func_assert_setLoadModeParallelAttempted	placeholdernameoftest
[l] VID_SP_func_assert_setLoadModeSerialAttempted	placeholdernameoftest
[D] VID_SP_func_assert_writeReqAfterOkToWrite	placeholdernameoftest
[D] VID_SP_func_assert_writeReqB4okToWrite	placeholdernameoftest
[D] VID_SP_func_assert_writeReqBeforeOkToWrite	placeholdernameoftest
[D] VID_SP_func_assert_writeReqWithdrawnOK	placeholdernameoftest
[D] VID_SP_func_assert_writeB4OKandReady_ERR
[l] VID_SP_func_self_OoOcompletes	placeholdernameoftest
[l] VID_SP_func_self_pipeline	placeholdernameoftest
[l] VID_SP_rand_assert_frameID_wOutMismatch_ERR	placeholdernameoftest
[D] VID_SP_func_assert_readyToReadLeadsReadReq_ERR	placeholdernameoftest
[D] VID_SP_func_assert_readyToWriteLeadsWriteReq_ERR	placeholdernameoftest
[l] VID_SP_rand_assert_cprop_abortWithinXYZ	placeholdernameoftest
[l] VID_SP_rand_assert_FillAndKeepFull	placeholdernameoftest
[l] VID_SP_rand_assert_FillThenDrain	placeholdernameoftest
[D] VID_SP_rand_assert_sillyRead	placeholdernameoftest
[l] VID_SP_rand_assert_SingleComputation	placeholdernameoftest
[l] VID_SP_rand_self_CMMDarg0onlyChange	placeholdernameoftest
[l] VID_SP_rand_cover_abort	placeholdernameoftest
[l] VID_SP_rand_self_OoOcompletes	placeholdernameoftest
[l] VID_SP_rand_self_pipeline	placeholdernameoftest

Current tests: