Basic UVM testbench for a Stream Processor
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Integrating new computations

 
 

How to integrate and test your own computational unit in the oneproc testbench

This is
WILL BE, when it's done,
a walkthrough of how to add a computational unit to the oneproc unit and the testbench. To be concrete for this walkthrough, I'll adding a new function, LFSR16X. Here is the "spec" for that function: 
Compute the 16 bit value of the serial B-bit string using the 16-bit LFSR
with taps specified by the bit pattern in {arg1,arg0}. 

A "1" in bitX means D[X+1] = Q[X] xor (inputbit XOR Q[15]) ;
A "0" in bitX means D[X+1] = Q[X] ;
Ex. To get CRC16 CCITT:
{arg1,arg0} 16'b0001_0000_0010_0001
addr00 frameID
addr01 CMMD
addr02 arg0
addr03 arg1
addr04 LFSR[15:8]
addr05 LFSR[7:0]
addr06 error_code
addr07 reserved
addr08-byte63, 56 bytes of Data.
Data is streamed in lsb-msb of addr08 to addr63

1. Determine if you can live with the write and read channels as they are.

2. Design the DataRec

CMMD, args, return values, error conditions, data or pointers

Choose oneproc internal memory size and databus widths.

Update dut_pkg.svh

3. Add a new sequence based on the CMMD name

The purpose of this sequence is to fill out the DataRec in a way that makes sense for the CMMD. This will probably not be extended from an existing test. It that were possible, then the DataRec would be so much like the parent that what you need might only be changes to arg0 and/or arg1.

4. Add a new test based on the CMMD name and some argument memonic

Point to the new sequence.

5. Include in the scoreboard a specific CMMD related read/write pair

6. Integrate, if needed, a C based reference model into the scoreboard

The scoreboard ought to have some way to report success/fail, so there needs to be criteria. So create a reference model of some sort that will provide expectations of correct behavior.

7. Build and run the test


 
 
 
This is a work in progress