`include "tb_pkg.svh"

import tb_pkg::*;

`define X_MINVAL  1
`define X_MAXVAL 100


class box_t;
  static int firsttime = 1 ;
  int theData;
  //             ------  NOT A COMMENT TO IGNORE  -------
  //  The constraint below is what I'd like to mimic, but SystemVerilog
  //  does not have an arbitrary distribution function. So I made one.
  //  constraint  the_index 
  //  { 
  //    theData $dist_arbitrary (`X_MINVAL, `X_MAXVAL);
  //  }
  //  Note that the variable 'theData' is NOT rand, because all the work
  //  happens on the C-side in pre-randomize and we can't have 'theData'
  //  being scrambled after its holiday visit to the C-side.


  function void pre_randomize();
    if (firsttime == 1)
    begin
      firsttime = 0 ;
      theData = dist_arb(0, `X_MINVAL, `X_MAXVAL) ; // theData here is tossed
    end
      theData = dist_arb(1, `X_MINVAL, `X_MAXVAL) ;
  endfunction : pre_randomize
endclass : box_t



module tb;
  int i = 0;
  box_t box = new();

  initial begin
    repeat (4500) 
    begin
      i = box.randomize();
      $write("\ntheData= %d", box.theData);
    end
  end
endmodule